The present invention relates to semiconductor packaging technology. The present invention has particular applicability to semiconductor packages containing a static random access memory (SRAM) die and to manufacturing such packages.
Ongoing advances in solid-state electronic devices impose continuous demands for integrated circuit devices with increased functionality, density, and performance. In response, multi-chip modules have evolved comprising a printed circuit board substrate to which a series of separate components are directly attached. Multi-chip devices advantageously increase circuit density with attendant improvements in signal propagation speed and overall device weight.
Integrated circuit devices are typically electronically packaged by mounting one or more chips to a ceramic, e.g., alumna circuitized substrate, sometimes referred to as a chip carrier. Wire bonds are employed to electrically connect input/output (IO) contact pads on each chip to corresponding contact pads and to corresponding fan-out circuitry on the circuitized chip carrier substrate. The resulting chip carrier is then typically mounted on a printed circuit board (PCB) and, employing circuitry on the PCB, electrically coupled to other such chip carriers and/or other electronic components mounted on the PCB.
Conventional circuitized substrates contain two or more layers of fan-out circuitry on two or more ceramic layers. Such layers of fan-out circuitry are electrically interconnected by mechanically drilled holes known as vias which are plated and/or filled with electrically conductive material, e.g., copper. Some of the holes extend from the layers of fan-out circuitry to respective lands on the chip carrier substrates, on which are mounted solder balls forming a grid array, thereby generating the expression xe2x80x9cball grid arrayxe2x80x9d. The solder balls are mechanically and electrically connected to corresponding solderable contact pads on the PCB.
The continuous increase in the size of large scale integrated circuit chips results in a corresponding increase in the number of I/O connections required to be made to a chip. The increase in the number of I/O connections results in an increase in process complexity since thin wires must be manually or automatically placed between the chips pads and the chip carrier pads for electrical connections.
The trend toward increased functionality, density and performance has also given rise to the practice of superimposing semiconductor dies on a chip carrier substrate. One such stacked die configuration contains a lower die comprising an SRAM semiconductor device and an upper die bonded to the lower die employing a conventional die attach material, such as a non-conductive epoxy resin. However, it was found that such stacked die configurations having a lower SRAM die exhibited an unusual high rejection rate in final reliability testing.
Accordingly, there exists a need for reliable stacked die circuit assembles containing a lower SRAM die. There also exist a need for methodology enabling the manufacture of stacked die circuit assemblies having a lower SRAM die exhibiting high reliability.
An advantage of the present invention is a highly reliable stacked die circuit assembly with a lower SRAM die.
Another advantage of the present invention is a method of manufacturing a reliable stacked die circuit assembly comprising a lower SRAM die.
Additional advantages and features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a circuit assembly comprising: a substrate having a main surface; a first die having an upper surface and a lower surface attached to the main surface of the substrate, the first die comprising a first polyimide coating on the upper surface of the first die, the first polyimide coating having a repair access opening exposing a portion of an upper surface of the first die; a polyimide material, different from the first polyimide coating, over the opening; and a second die attached to the upper surface of the first die with the first polyimide coating and the polyimide material therebetween.
Another aspect of the present invention is a method of manufacturing a circuit assembly, the method comprising: attaching a lower surface of a first die to a main surface of a substrate, the first die having an upper surface opposite the lower surface and a first polyimide coating on the upper surface of the first die, wherein the first polyimide coating has a repair access opening therein exposing a portion of the upper surface of the first die; covering at least part of the exposed upper portion of the first die with polyimide material; and die attaching a second die to the upper surface of the first die with the first polyimide coating and the polyimide material therebetween.
Embodiments of the present invention comprise a circuit assembly having a lower die comprising an SRAM device with a polyimide coating thereon having a thickness of less than about 1 mil. The polyimide coating has a repair access opening exposing a thin silicon nitride passivation film of the SRAM device. Embodiments of the present invention include covering at least a portion of the exposed silicon nitride passivation film with a solid piece of polyimide loosely or tightly fitting within the repair access opening. Another embodiment of the present invention comprises spraying an additional polyimide coating, having a thickness less than about 1 mil, on the first polyimide coating and into the repair access opening covering the exposed portion of the silicon nitride passivation film.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawing and description is to be regarded as illustrative in nature, and not as restrictive.